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? semiconductor components industries, llc, 2017 december, 2017 ? rev. 1 1 publication order number: NCP5183/d NCP5183, ncv5183 high voltage high current high and low side driver the NCP5183 is a high voltage high current power mosfet driver providing two outputs for direct drive of 2 n?channel power mosfets arranged in a half?bridge (or any other high?side + low?side) configuration. it uses the bootstrap technique to insure a proper drive of the high?side power switch. the driver works with 2 independent inputs to accommodate any topology (including half?bridge, asymmetrical half?bridge, active clamp and full?bridge ? ). features ? automotive qualified to aec q100 ? voltage range: up to 600 v ? dv/dt immunity 50 v/ns ? gate drive supply range from 9 v to 18 v ? output source / sink current capability 4.3 a / 4.3 a ? 3.3 v and 5 v input logic compatible ? extended allowable negative bridge pin voltage swing to ?10 v ? matched propagation delays between both channels ? propagation delay 120 ns typically ? under v cc lockout (uvlo) for both channels ? pin to pin compatible with industry standards ? these are pb?free devices typical application ? power supplies for telecom and datacom ? half?bridge and full?bridge converters ? push?pull converters ? high voltage synchronous?buck converters ? motor controls ? electric power steering ? class?d audio amplifiers www.onsemi.com ordering information device package shipping ? NCP5183dr2g soic?8 (pb?free) 2500 / tape & reel soic?8 nb case 751?07 marking diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. pin connections hin lin gnd drvl vcc drvh vb hb 1 8 ncx5183 alyw 1 8 x = p or v a = assembly location l = wafer lot y = year w = work week = pb?free package ncv5183dr2g soic?8 (pb?free) 2500 / tape & reel (note: microdot may be in either location)
NCP5183, ncv5183 www.onsemi.com 2 figure 1. application schematic c vcc m1 m2 c boot 8 5 6 7 1 2 3 4 vb drvh hb vcc hin lin gnd drvl controller vcc v hv load d boot r boot figure 2. simplified block diagram level shifter pulse trigger s r q q uv detect drvh hb vb drvl v cc hin v cc lin gnd delay uv detect table 1. pin function description pin no. (soic8) pin name description 1 hin high side logic input 2 lin low side logic input 3 gnd ground 4 drvl low side gate drive output 5 v cc main power supply 6 hb bootstrap return or high side floating supply return 7 drvh high side gate drive output 8 vb bootstrap power supply
NCP5183, ncv5183 www.onsemi.com 3 table 2. absolute maximum ratings all voltages are referenced to gnd pin rating symbol value units input voltage range v cc ?0.3 to 18 v input voltage on lin and hin pins v lin , v hin ?0.3 to 18 v high side boot pin voltage v b (higher of {?0.3 ; v cc ? 1.5}) to 618 v high side bridge pin voltage v hb v b ? 18 to v b + 0.3 v high side floating voltage v b ? v hb ?0.3 to 18 v high side output voltage v drvh v hb ? 0.3 to v b + 0.3 v low side output voltage v drvl ?0.3 to v cc + 0.3 v allowable output slew rate dv hb /dt 50 v/ns maximum operating junction temperature t j(max) 150 c storage temperature range tstg ?55 to 150 c esd capability, human body model (note 1) esdhbm 3 kv esd capability, charged device model (note 1) esdcdm 1 kv lead temperature soldering reflow (smd styles only), pb?free versions (note 2) t sld 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (eia/jesd22?a114) esd charged device model tested per aec?q100?11 (eia/jesd22?c101e) latchup current maximum rating: 150 ma per jedec standard: jesd78 2. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d table 3. thermal characteristics rating symbol value units thermal characteristics so8 (note 3) thermal resistance, junction?to?air (note 4) r ja 183 c/w 3. refer to electrical characteristics and application information for safe operating area. 4. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. table 4. recommended operating conditions (note 5) all voltages are referenced to gnd pin rating symbol min max units input voltage range v cc 10 17 v high side floating voltage v b ? v hb 10 17 v high side bridge pin voltage v hb ?1 580 v high side output voltage v drvh v hb v b v low side output voltage v drvl gnd v cc v input voltage on lin and hin pins v lin , v hin gnd v cc ? 2 v operating junction temperature range t j ?40 125 c 5. refer to electrical characteristics and application information for safe operating area.
NCP5183, ncv5183 www.onsemi.com 4 table 5. electrical characteristics ?40 c t j 125 c, v cc = v b = 15 v, v hb = gnd, outputs are not loaded, all voltages are referenced to gnd; unless otherwise noted. typical values are at t j = +25 c. (notes 6, 7) parameter test conditions symbol min typ max units supply section v cc uvlo v cc rising v ccon 7.8 8.8 9.8 v v cc falling v ccoff 7.2 8.3 9.1 v v cc hysteresis v cchyst 0.5 v v b uvlo v b rising v bon 7.8 8.8 9.8 v v b falling v boff 7.2 8.3 9.1 v v b hysteresis v bhyst 0.5 v v cc pin operating current f = 20 khz, c l = 1 nf i cc1 520 700 a v b pin operating current f = 20 khz, c l = 1 nf i b1 700 800 a v cc pin quiescent current v lin = v hin = 0 v i cc2 95 160 a v b pin quiescent current v lin = v hin = 0 v i b2 65 100 a v b to gnd quiescent current v b = v hb = 600 v i hsleak 50 a input section logic high input voltage v inh 2.5 v logic low input voltage v inl 1.2 v logic high input current v xin = 5 v i xin+ 25 50 a logic low input current v xin = 0 v i xin? 1 a input pull down resistance v xin = 5 v r xin 100 250 k output section low level output voltage i drvl = 0 a v drvll 35 mv low level output voltage (hs driver) i drvh = 0 a v drvhl 35 mv high level output voltage i drvl = 0 a, v drvlh = v cc ? v drvl v drvlh 35 mv high level output voltage (hs driver) i drvh = 0 a, v drvhh = v b ? v drvh v drvhh 35 mv output positive peak current v drvl = 0 v, pw = 10 s i drvlh 4.3 a output negative peak current v drvl = 15 v, pw = 10 s i drvll 4.3 a output positive peak current (hs driver) v drvh = 0 v, pw = 10 s i drvhh 4.3 a output negative peak current (hs driver) v drvh = 15 v, pw = 10 s i drvhl 4.3 a output resistance r oh 1.7 output resistance r ol 1.1 dynamic section turn on propagation delay t on 120 200 ns turn off propagation delay t off 120 200 ns delay matching pulse width = 1 s t mt 0 50 ns minimum positive pulse width v xin = 0 v to 5 v t minh 150 ns minimum negative pulse width v xin = 5 v to 0 v t minl 100 ns 6. refer to absolute maximum ratings and application information for safe operating area 7. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible
NCP5183, ncv5183 www.onsemi.com 5 table 5. electrical characteristics ?40 c t j 125 c, v cc = v b = 15 v, v hb = gnd, outputs are not loaded, all voltages are referenced to gnd; unless otherwise noted. typical values are at t j = +25 c. (notes 6, 7) parameter units max typ min symbol test conditions switching parameters output voltage rise time 10% to 90%, c l = 1 nf t r 12 40 ns output voltage fall time 90% to 10%, c l = 1 nf t f 12 40 ns negative hb pin voltage pw t on , v cc = v b = 10 v v hbneg ?8 ?7 v 6. refer to absolute maximum ratings and application information for safe operating area 7. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible figure 3. propagation delay, rise time and fall time timing drvl, drvh lin, hin 50% 90% 10% t on t off t r t f figure 4. delay matching hin, lin drvx 10% 90% drvx 10% 90% lin (hin) 10% 90% drvx 10% 90% t mt hin (lin) drvx t mt t mt t mt t mt t mt t mt t mt
NCP5183, ncv5183 www.onsemi.com 6 figure 5. v ccon vs. temperature figure 6. v ccoff vs. temperature figure 7. v ccuvlohys vs. temperature figure 8. v bon vs. temperature figure 9. v boff vs. temperature figure 10. v bhyst vs. temperature
NCP5183, ncv5183 www.onsemi.com 7 figure 11. i cc1 vs. temperature figure 12. i cc2 vs. temperature figure 13. i b1 vs. temperature figure 14. i b2 vs. temperature figure 15. i hsleak vs. temperature figure 16. r in vs. temperature
NCP5183, ncv5183 www.onsemi.com 8 figure 17. t on vs. temperature figure 18. t off vs. temperature figure 19. t r vs. temperature figure 20. t f vs. temperature figure 21. t r for 10 nf load vs. temperature figure 22. t f for 10 nf load vs. temperature figure 23. r oh vs. temperature figure 24. r ol vs. temperature
NCP5183, ncv5183 www.onsemi.com 9 figure 25. t mt vs. temperature figure 26. i cc and i b current consumption vs. frequency
NCP5183, ncv5183 www.onsemi.com 10 mosfet turn on and turn off current path a capacitor connected from vcc (vb) to gnd (hb) terminal is source of energy for charging the gate terminal of an external mosfet(s). for better understanding of this process see figure 27 (all voltages are related to gnd (hb) pin). when there is a request from internal logic to turn on the external mosfet, then the q source is turned on. the current starts to flow from c vcc (c boot ), through q source , gate resistor r g to the gate terminal of the external mosfet (depictured by red line). the current loop is closed from external mosfet source terminal back to the c vcc (c boot ) capacitor. after a while the c gs capacitance is fully charged so no current flows this path. when the external mosfet going to be turned off, the internal q source is turned off first and after a short dead time q sink is turned on. then c vcc (c boot ) is not a source any more, the source of energy became the c gs (and all capacitance connected to this terminal, like muller capacitance). now the current flows from gate terminal, through r g resistor and q sink back to the mosfet (depictured by blue line). in both cases (charging and discharging external mosfet) there are several parasitic inductances in the path. all of them play a role during switching. in figure 27 an influence of the inductances in some places is showed. on vcc (vb) pin a drop during turn on and turn off is observed. if too long an uvlo protection can be triggered and the driver can be turned off subsequently, which result in improper operation of the application. figure 27. equivalent circuit of power switch driver vcc(vb) drvl(drvh) gnd(hb) c vcc (c boot ) c gd c gs r dson q source q sink r dson r g l bond l bond l bond l trace l trace l trace l trace mosfet i turn on i turn off NCP5183 all voltages are refered to gnd (hb) pin turn on turn off turn on turn off turn on turn off turn on turn off voltage probes
NCP5183, ncv5183 www.onsemi.com 11 layout recommendation the NCP5183 is high speed, high current (sink/source 4.3 a/4.3 a) driver suitable for high power application. to avoid any damage and/or malfunction during switching (and/or during transients, overloads, shorts etc.) it is very important to avoid a high parasitic inductances in high current paths (see ?mosfet turn on and turn off current path? section). it is recommended to fulfill some rules in layout. one of a possible layout for the ic is depictured in figure 28. ? keep loop hb_pin ? gnd_pin ? q_lo as small as possible. this loop (parasitic inductance) has potential to increase negative spike on hb pin which can cause of malfunction or damage of hb driver. the negative voltage presented on hb pin is added to v cc ?v f voltage so v cboot is increased. in extreme case the c boot voltage can be so high it will reach maximum rating value which can lead to device damage. ? keep loop vdd_pin ? gnd_pin ? c vcc as small as possible. the ic featured high current capability driver. any parasitic inductance in this path will result in slow q_lo turn on and voltage drop on vcc pin which can result in uvlo activation. ? keep loop vb_pin ? hb_pin ? c boot as small as possible. the ic featured high current capability driver. any parasitic inductance in this path will result in slow q_hi turn on and voltage drop on vb pin which can result in uvlo activation. ? do not let high current flow through trace between gnd_pin and c vcc even a small parasitic inductance here will create high voltage drop if high current flows through this path. this voltage is added or subtracted from hin and lin signal, which results in incorrect thresholds or device damaging. ? keep loops drvl_pin ? q_lo ? gnd_pin and drvh_pin ? q_hi ? hb_pin as small as possible. a high parasitic inductance in these paths will result in slow mosfet switching and undesired resonance on gate terminal. figure 28. recommended layout
NCP5183, ncv5183 www.onsemi.com 12 c boot capacitor value calculation the device featured two independent 4.3 a sink and source drivers. the low side driver (drvl) supplies a mosfet whose source is connected to ground. the driver is powered from v cc line. the high side driver (drvh) supplies a mosfet whose source is floating from gnd to bulk voltage. the floating driver is powered from c boot capacitor. the capacitor is charged only when hb pin is pulled to gnd (by inductance or the low side mosfet when turned on). if too small c boot capacitor is used the high side uvlo protection can disable the high side driver which leads to improper switching. expected voltage on c boot is depictured in figure 29. the curves are valid for zvs (zero v oltage switching) observed in llc applications. for hard switch the curves are slightly different, but from charge on c boot point of view more favorable. under the hard switch conditions the energy to charge q g (from zero voltage to v th of the mosfet) is taken from v cc capacitor (through an external boot strap diode) so the voltage drop on c boot is smaller. for the calculation of c boot value the zvs conditions are taken account. the switching cycle is divided into two parts, the char ging (t charge ) and the discharging (t discharge ) of the c boot capacitor. the discharging can be divided even more to discharging by floating driver current consumption i b2 (t dsib ) and to discharging by transfering energy from c boot to gate terminal of the mosfet (t dsqm ). discharg ing by i b2 becoming more dominant when driver runs at lower frequencies and/or during skip mode operation. to calculate c boot value, follow these steps: figure 29. boot strap capacitor charging principle 1. for example, let?s have a mosfet with q g = 30 nc, v dd = 15 v. 2. charge stored in c boot necessary to cover the period the c boot is not supplied from v cc line (which is basically the period the high side mosfet is turned on). let?s say the application is switching at 100 khz, 50% duty cycle, which means the upper mosfet is conductive for 5 s. it means the c boot is discharged by i b2 current (81 a typ) for 5 s, so the charge consumed by floating driver is: q b i b2 t discharge 81 5 405 pc (eq. 1) 3. total charge loss during one switching cycle is sum of charge to supply the high side driver and mosfet?s gate charge: q tot q g q b 30n 405p 30.4 nc (eq. 2)
NCP5183, ncv5183 www.onsemi.com 13 4. let?s determine acceptable voltage ripple on c boot to 1% of nominal value, which is 150 mv. to cover charge losses from eq. 2 c boot q tot v ripple 30.4n 0.15 203 nf (eq. 3) it is recommended to increase the value as consumption and gate charge are temperature and voltage dependent, so let?s choose a capacitor 330 nf in this case. r boot resistor value calculation to keep the application running properly, it is necessary to charge the c boot again. this is done by external diode from v cc line to vb pin. in serial with the diode a resistor is placed to reduce the current peaks from v cc line. the resistor value selection is critical for proper function of the high side driver. if too small high current peaks are drown from v cc line, if too high the capacitor will not be charged to appropriate level and the high side driver can be disabled by internal uvlo protection. first of all keep in mind the capacitor is charged through the external boot strap diode, so it can be charged to a maximum voltage level of v cc ? v f . the resistor value is calculated using this equation: r boot t charge c boot ln v max v cmin v max v cmax 5 330n ln 14.4 14.2 14.4 14.35 (eq. 4) 11 where: t charge ? time period the c boot is being char ged, usually the period the low side mosfet is turned on c boot ? boot strap capacitor value v max ? maximum voltage the c boot capacitor can be theoretically charged to. usually the v cc ? v f . the v f is forward voltage of used diode. v cmin ?the voltage level the capacitor is charged from v cmax ?the voltage level the capacitor is charged to. it is necessary to determine the target voltage for charging, because in theory, when a capacitor is charged from a voltage source through a resistor, the capacitor can never reach the voltage of the source. in this particular case a 50 mv difference (between the voltage behind the diode and v cmax ) is used. the resistor value obtained from eq. 4 does not count with the quiescent current i b2 of the high side driver. this current will create another voltage drop of: v ib2_drop r boot i b2 11 81 0.9 mv (eq. 5) the current consumed by high side driver will be higher, because the i b2 is valid when the device is not switching. while switching, losses by charging and discharging internal transistors as well as the level shifters will be added. this current will increase with frequency. the additional 0.9 mv drop will be added to v cmax value. the additional 0.9 mv drop can be either accepted or the r boot value can be recalculated to eliminate this additional drop. the resistor r boot calculated in eq. 4 is valid under steady state conditions. during start and/or skip operation the starting point voltage value is different (lower) and it takes more time to charge the boot str ap capacitor. more over it is not counted with temperature and voltage variability during normal operation or the dynamic resistance of the boot strap diode (approximately 0.34 for mura160). from these reasons the resistor value should be decreased especially with respect to skip operation. boot strap resistor losses calculation. p rboot q tot v cmax f 30.4n 14.4 100k 44 mw (eq. 6 ) boot strap diode losses calculation. p dboot q tot v f f 30.4n 0.6 100k 1.8 mw (eq. 7) please keep in mind the value is temperature and voltage dependent. especially c boot voltage can be higher than calculated value. see ?layout recommendation? section for more details. total power dissipation the NCP5183 is suitable to drive high input capacitance mosfet, from this reason it is equipped with high current capability drivers. power dissipation on the die, especially at high frequencies can be limiting factor for using this driver. it is important to not exceed maximum junction temperature (listed in absolute maximum ratings table) in any cases. to calculate approximate power losses follow these steps: 1. power loss of device (except drivers) while switching at appropriate frequency (see figure 26) is equal to p logic p hs p ls (v boot i b2 ) (v cc i cc2 ) (eq. 8) (14.4 1.6m) (15 0.6m) 32.1 mw 2. power loss of drivers p drivers (q g v boot ) (q g v cc ) f (eq. 9) ( (30n 14.4) (30n 15) ) 100k 88 mw 3. total power losses p total p logic p drivers 32.1m 88m 120 mw (eq. 10) 4. junction temperature increase for calculated power loss t j r tja p total 183 0.12 22 k (eq. 11) the temperature calculated in eq. 11 is the value which has to be added to ambient temperature. in case the ambient temperature is 30 c, the junction temperature will be 52 c.
NCP5183, ncv5183 www.onsemi.com 14 package outline soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
NCP5183, ncv5183 www.onsemi.com 15 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP5183/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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